1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a memory circuit technology preferably for a memory device having a comparing (matching detection) capability.
2. Description of the Related Art
In a computer system such as a main computer, microprocessor or the like, a cache memory system for storing a part of the data in a main memory is used between a central processing unit (CPU) and the main memory for speed-up of operation of the computer system.
In this cache memory system, two types of memory devices having a comparing (matching detection) capability are used. Such types of memory devices determine whether or not a comparison data inputted externally matches with data stored in a first memory cell array, then accessing of a separately arranged second memory cell array is effected based on the result of the comparison. Therefore, they function as a CAM (Content Address Memory).
A first type of cache memory is an address translation cache memory for supporting a virtual memory system. In the address translation cache memory, a logical address of an instruction or data required by a central processor unit and the like is inputted to the first memory cell array to determine whether corresponding physical address is present in the second memory cell array. The physical address in accordance with the determination and a result of the comparison are then outputted from the second memory cell array. The address translation cache is also referred, to as TLB (Translation Look-aside Buffer) in which a logical address of data from the central processing unit is inputted to the first memory cell array (LA) and a detection is carried out of whether or not the logical address of data is a match with a logical address already stored the first memory cell array (LA). By this matching, that is detection operation, a determination is made of whether or not the physical address corresponding to the logical address inputted to the first memory array (LA) is present in the second memory cell array (PA) for storing the physical address. The physical address in accordance with the determination and the result of the determination are outputted from the second memory cell array.
A second type of cache memory stores a part of an instruction or data stored in the main memory device with the physical address to thereby be an instruction or data cache memory serving as a high speed buffer memory. By inputting the physical address to the first memory cell array, a determination is made of whether or not a corresponding instruction or data is present in the second memory cell array. The instruction or data in accordance with the determination and the result of the determination are outputted from the second memory cell array.
As mentioned above, a CAM or cache memory should be capable of comparing comparison input data with data already stored in the first memory array and outputting a result of determination of whether or not the input data and stored data are a match.
A conventional approach for achieving a comparison function (matching detection function), is exemplified by the comparator circuit coupled to respective memory cells, such as, disclosed in Japanese Patent Application Publication No. JP-A-63-25889.
Another known approach uses a circuit of the type in which a comparator circuit for comparing input data with data stored in a memory cell is provided between the memory cell and a sensing circuit to thereby provide a wired logical operation in accordance with an output signal from the sensing circuit, then a comparison result of n-bits is effected. Such an arrangement is disclosed in Japanese Patent Application Publication No. JP-A-63-119096.
In the circuit described in Japanese Patent Application Publication No. JP-A-63-119096, since read data (having a very small voltage swing) of a signal outputted from the memory cell on a data line is compared with input data to be compared, it is possible to operate the circuit at high speed. Since the data being inputted to the comparator circuit is without amplification. In addition, in this circuit, it suffices to connect a differential sensing circuit to each bit of the memory array via the comparator circuit. Therefore, the circuit system has advantages in that an occupied area of the circuit and its power consumption can be reduced in comparison with the above-mentioned system which carries out a detection of matching. That is, the detection of matching is carried out in the comparator circuit after converting readout data from the memory cell array into a certain level because both the differential sensing circuit and the amplifying level converting circuit are arranged for each bit of the memory cell array.